Power transistors are usually mounted onto a leadframe, i.e., a metal carrier. The leadframe serves primarily for stabilizing the power transistor including a semiconductor chip. The leadframe is furthermore used for making contact with the semiconductor chip.
FIGS. 1A and 1B show an example of a power transistor mounted in this way. A power transistor 1 has a leadframe 2, a semiconductor chip 3 arranged on the leadframe 2, and a housing 4 that protects the semiconductor chip 3. An insulation layer 5 is provided beneath the leadframe 2 and electrically insulates the leadframe 2 from a heat sink 6. Contact is made with the top side of the semiconductor chip 3 via one or more bonding wires 7 led out from the housing 4 as connection 8. A source contact-making layer 9 and a gate contact-making layer 10, which are insulated from one another, are provided on the top side of the semiconductor chip 3. Contact is made with the gate contact-making layer 10 by one or more bonding wires 11 led out from the housing 4 as connection 12.
The power transistor 1 shown in FIGS. 1A and 1B is a vertical MOSFET (metal oxide semiconductor field effect transistor) configured as an n-channel transistor. In this example, the leadframe 2 forms the drain contact-making layer of the semiconductor chip 3 or serves as electrical connection of a drain contact-making layer formed on the underside of the semiconductor chip 3. The leadframe 2 is mechanically and electrically connected to the underside of the semiconductor chip 3 by soldering material or an adhesive.
FIG. 1C shows an applied example of the power transistor 1 shown in FIGS. 1A and 1B, a bridge circuit 20. In the bridge circuit 20, four transistors T1, T2, T3, T4 are connected to one another as shown. The power transistor identified by reference numeral T4 in this case corresponds to the power transistor 1 shown in FIGS. 1A and 1B.
What is disadvantageous about the power transistor 1 shown in FIGS. 1A and 1B is that when the power transistor is used as a low-side switch, the leadframe 2 is connected to an electrical load and thus has to be electrically insulated from the heat sink 6, which is generally at ground. If an insulation layer 5 of this type were not provided, an electrical short circuit would occur between the leadframe 2 and the heat sink 6. Accordingly, the insulation layer 5 is necessary and brings about additional costs, additional mounting complexity, and an impairment of the thermal cooling properties of the power transistor 1. The same problems occur, if the power transistor 1 is used in half-bridges or full-bridges.
In order to avoid this disadvantage, it is known, as shown in FIGS. 2A and 2B, to mount the semiconductor chip 3 onto the leadframe 2 such that the top side of the semiconductor chip 3 is formed by a drain contact-making layer 13 and the underside of the semiconductor chip 3 is formed by the source contact-making layer 9 and the gate contact-making layer 10. The semiconductor chip 3 is mounted onto the leadframe 2 in “reversed” fashion. In order to contact the source contact-making layer 9 and the gate contact-making layer 10, the leadframe 2 of the power transistor 1′ shown in FIGS. 2A and 2B is divided into two parts, i.e., the leadframe includes a first part 2a and a second part 2b that are insulated from one another. The first part of the leadframe 2a is led out from the housing 4 via a connection 14, and the second part 2b of the leadframe is led out from the housing 4 via the connection 12. The bonding wires 7 contact the drain contact-making layer 13 of the semiconductor chip 3 and are led out from the housing 4 in the form of the connection 8.
If the power transistor 1′ is used as a low-side switch, the power transistor 1′ omits the insulation layer 5 between the leadframe 2 and the heat sink 6, i.e., insulation between the first part 2a of the leadframe 2 and the heat sink is omitted, and the second part 2b of the leadframe is electrically insulated from the heat sink 6. The insulation layer 5 is no longer necessary since both the source contact-making layer 9, i.e., the underside of the semiconductor chip 3, and the first part 2a of the leadframe are at ground, whereby no potential difference occurs between the underside of the semiconductor chip 3 and the heat sink 6 (which is also at ground).
In this case, the semiconductor chip 3 is applied to the leadframe 2 by diffusion soldering processes or adhesive-bonding processes; conventional soldering processes are virtually never used. The drain contact-making layer 13 is electrically connected to the connection 8 by applying bonding wires or by soldering with an iron.
FIG. 2C discloses another example of the power transistor 1′ shown in FIGS. 2A and 2B, which corresponds to the bridge circuit example shown in FIG. 1B.
A disadvantage of the power transistor 1′ shown in FIGS. 2A and 2B is that contact is made with the underside of the semiconductor chip 3 by a leadframe divided into two parts, which is relatively complicated to produce, rather than by wire bonding processes that can be carried out in a simple manner (see above). It would be desirable to contact the drain contact-making layer 13 and the gate contact-making layer 10 equally by a wire bonding contact method that can be carried out in a simple manner.
A power transistor that does not require an insulation layer between the leadframe and the heat sink and provides contact in a simple manner is desirable.